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? 2008 microchip technology inc. ds21949c-page 1 tc1303a/tc1303b/ tc1303c/tc1304 features dual-output regulator (500 ma buck regulator and 300 ma low-dropout regulator) power-good output with 300 ms delay total device quiescent current = 65 a, typical independent shutdown for buck and ldo outputs ( tc1303 ) both outputs internally compensated synchronous buck regulator: - over 90% typical efficiency - 2.0 mhz fixed-frequency pwm (heavy load) - low output noise - automatic pwm to pfm mode transition - adjustable (0.8v to 4.5v) and standard fixed-output voltages (0.8v, 1.2v, 1.5v, 1.8v, 2.5v, 3.3v) low-dropout regulator: - low-dropout voltage = 137 mv typical @ 200 ma - standard fixed-output voltages (1.5v, 1.8v, 2.5v, 3.3v) power-good function: - monitors buck output function ( tc1303a ) - monitors ldo output function ( tc1303b ) - monitors both buck and ldo output functions ( tc1303c and tc1304 ) - 300 ms delay used for processor reset sequenced startup and shutdown ( tc1304 ) small 10-pin 3x3 dfn or msop package options operating junction temperature range: - -40c to +125c undervoltage lockout (uvlo) output short circuit protection overtemperature protection applications cellular phones portable computers usb-powered devices handheld medical instruments organizers and pdas description the tc1303/tc1304 combines a 500 ma synchronous buck regulator and 300 ma low-dropout regulator (ldo) with a power-good monitor to provide a highly integrated solution for devices that require multiple supply voltages. the unique combination of an integrated buck switching regulator and low-dropout linear regulator provides t he lowest system cost for dual-output voltage applications that require one lower processor core voltage and one higher bias voltage. the 500 ma synchronous buck regulator switches at a fixed frequency of 2.0 mhz when the load is heavy, providing a low noise, small-size solution. when the load on the buck output is reduced to light levels, it changes operation to a pulse frequency modulation (pfm) mode to minimize qu iescent current draw from the battery. no intervention is necessary for smooth transition from one mode to another. the ldo provides a 300 ma auxiliary output that requires a single 1 f ceramic output capacitor, minimizing board area and cost. the typical dropout voltage for the ldo output is 137 mv for a 200 ma load. for the tc1303/tc1304, the power-good output is based on the regulation of the buck regulator output, the ldo output or the combination of both. the tc1304 features start-up and shutdown output sequencing. the tc1303/tc1304 is available in either the 10-pin dfn or msop package. additional protection features include: uvlo, overtemperature and overcurrent protection on both outputs. for a complete listing of tc1303/tc1304 standard parts, consult your microchip representative. 500 ma synchronous buck regulator, + 300 ma ldo with power-good output downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 2 ? 2008 microchip technology inc. package types 10-lead dfn v fb1 /v out1 10-lead msop 12 6 8 7 9 10 5 4 3 shdn2 v in2 v out2 a gnd p gnd lxvin1 shdn1 v fb1 /v out1 pg 10-lead dfn 10-lead msop 12 6 8 7 9 10 5 4 3 shdn v in2 v out2 a gnd p gnd l x v in1 v fb1 /v out1 pg a gnd tc1303a,b,c tc1304 v out2 v in2 pg l x v in1 1 2 3 4 10 9 8 7 shdn1 p gnd shdn2 ep 11 5 6 a gnd v fb1 /v out1 v out2 v in2 pg l x v in1 1 2 3 4 10 9 8 7 a gnd p gnd shdn ep 11 5 6 a gnd downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 3 tc1303a/tc1303b/tc1303c/tc1304 functional block diagram C tc1303 synchronous buck regulator ndrv pdrv p gnd v in1 l x driver p gnd control v out1 /v fb1 v in2 shdn1 pg v ref ldo v out2 a gnd a gnd p gnd undervoltage lockout uvlo uvlo shdn2 v ref tc1303a (1) ,b (2) ,c (1) options pg generator with delay (uvlo) sense ldo for b,c sense switcher for a,c note 1: pg open-drain for a,c options 2: pg push-pull output for b option downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 4 ? 2008 microchip technology inc. functional block diagram C tc1304 synchronous buck regulator ndrv pdrv p gnd v in1 l x driver p gnd control v out1 /v fb1 v in2 shdn pg v ref ldo v out2 a gnd a gnd p gnd undervoltage lockout uvlo uvlo v ref tc1304 (note) pg generator with delay (uvlo) output voltage sequencer ckt. a gnd note: pg open-drain for tc1304 downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 5 tc1303a/tc1303b/tc1303c/tc1304 typical application circuits 10-lead dfn 1 2 6 87 9 10 5 4 3 shdn2 v in2 v out2 a gnd p gnd l x v in1 shdn1 v out1 pg 4.7 f processor reset input voltage 4.7 h 4.7 f 2.1v @ 1 f 3.3v @ 4.5v to 5.5v adjustable-output application 121 k ? 200 k ? 4.99 k ? 33 pf 1 2 6 87 9 10 5 4 3 shdn2 v in2 v out2 a gnd p gnd l x v in1 shdn1 v out1 pg 4.7 f processor reset 4.7 h 4.7 f 1.5v @ 500 ma 1 f 2.5v @ 300 ma 2.7v to 4.2v tc1303b v out1 v out2 v in v out1 v out2 1.0 f *optional capacitor v in2 300 ma 500 ma note: connect dfn package exposed pad to a gnd . 10-lead msop fixed-output application tc1303a (note) r pullup 1 2 6 87 9 10 5 4 3 shdn v in2 v out2 a gnd p gnd l x v in1 v out1 pg 4.7 f processor reset 4.7 h 4.7 f 1.2v @ 500 ma 1 f 2.5v @ 300 ma 2.7v to 4.2v v out1 v out2 v in 10-lead msop fixed-output application tc1304 r pullup a gnd ep 11 downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 6 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 7 tc1303a/tc1303b/tc1303c/tc1304 1.0 electrical characteristics absolute maximum ratings ? v in - a gnd .......................................................................6.0v all other i/o ...............................(a gnd - 0.3v) to (v in + 0.3v) l x to p gnd ...............................................-0.3v to (v in + 0.3v) p gnd to a gnd .................................................. -0.3v to +0.3v output short circuit current ................................ continuous power dissipation ( note 7 ) .......................... internally limited storage temperature .....................................-65c to +150c ambient temp. with power applied ................-40c to +85c operating junction temperature...................-40c to +125c esd protection on all pins (hbm) ....................................... 3kv ? notice: stresses above those listed under maximum ratings may cause permanent dam age to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: v in1 =v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l = 4.7 h, v out1 (adj) = 1.8v, i out1 = 100 ma, i out2 = 0.1 ma t a = +25c. boldface specifications apply over the t a range of -40c to +85c . parameters sym min typ max units conditions input/output characteristics input voltage v in 2.7 5.5 v note 1 , note 2, note 8 maximum output current i out1_max 500 m a note 1 maximum output current i out2_max 300 m a note 1 shutdown current combined v in1 and v in2 current i in_shdn 0.05 1 a shdn1 =shdn 2=gnd tc1303a,b operating i q tc1303c , tc1304 operating i q i q i q 65.0 70.1 110 110 a shdn1 =shdn 2=v in2 i out1 =0ma, i out2 =0ma synchronous buck i q 38 a shdn1 = v in , shdn2 = gnd ldo i q 46 a shdn1 = gnd, shdn2 = v in2 shutdown/uvlo/thermal shutdown characteristics shdn 1,shdn2 , shdn ( tc1304 ) logic input voltage low v il 15 %v in v in1 =v in2 = 2.7v to 5.5v shdn 1,shdn2 , shdn ( tc1304 ) logic input voltage high v ih 45 % v in v in1 =v in2 = 2.7v to 5.5v shdn 1,shdn2 , shdn ( tc1304 ) input leakage current i in -1.0 0.01 1.0 a v in1 =v in2 = 2.7v to 5.5v shdnx =gnd shdny =v in thermal shutdown t shd 165 c note 6 , note 7 thermal shutdown hysteresis t shd-hys 1 0 c undervoltage lockout (v out1 and v out2 ) uvlo 2.4 2.55 2.7 vv in1 falling undervoltage lockout hysteresis uvlo - hys 200 mv note 1: the minimum v in has to meet two conditions: v in 2.7v and v in v rx + v dropout, v rx = v r1 or v r2 . 2: v rx is the regulator output voltage setting. 3: tcv out2 = ((v out2max C v out2min ) * 10 6 )/(v out2 * d t ). 4: regulation is measured at a constant junction temperature using low duty-cycle pulse testing. load regulation is tested over a load range from 0.1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1v differential. 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. t a , t j , ja ). exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. 7: the integrated mosfet switches hav e an integral diode from the l x pin to v in , and from l x to p gnd . in cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. thermal protection is not able to limit the junction temperature for these cases. 8: v in1 and v in2 are supplied by the same input source. downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 8 ? 2008 microchip technology inc. synchronous buck regulator (v out1 ) adjustable output voltage range v out1 0.8 4.5 v adjustable reference feedback voltage (v fb1 ) v fb1 0.78 0.8 0.82 v feedback input bias current ( ifb1 ) i vfb1 - 1 . 5 n a output voltage tolerance fixed (v out1 ) v out1 -2.5 0.3 +2.5 % note 2 line regulation (v out1 )v line-reg 0.2 %/v v in =v r +1v to 5.5v, i load = 100 ma load regulation (v out1 )v load-reg 0 . 2 %v in =v r +1.5v, i load = 100 ma to 500 ma ( note 1 ) dropout voltage v out1 v in C v out1 280 mv i out1 = 500 ma, v out1 =3.3v ( note 5 ) internal oscillator frequency f osc 1.6 2.0 2.4 mhz start up time t ss 0 . 5 m st r = 10% to 90% r dson p-channel r dson-p 450 m i p =100 ma r dson n-channel r dson-n 450 m i n =100 ma l x pin leakage current i lx -1.0 0.01 1.0 a shdn = 0v, v in = 5.5v, l x = 0v, l x = 5.5v positive current limit threshold +i lx(max) 700 ma ldo output (v out2 ) output voltage tolerance (v out2 )v out2 -2.5 0.3 +2.5 % note 2 temperature coefficient tcv out 25 ppm/c note 3 line regulation ? v out2 / ? v in -0.2 0.02 +0.2 %/v (v r +1v) v in 5.5v load regulation, v out2 2.5v ? v out2 / i out2 -0.75 -0.08 +0.75 %i out2 = 0.1 ma to 300 ma ( note 4 ) load regulation, v out2 < 2.5v ? v out2 / i out2 -0.9 -0.18 +0.9 %i out2 = 0.1 ma to 300 ma ( note 4 ) dropout voltage v out2 > 2.5v v in C v out2 137 205 300500 mv i out2 = 200 ma ( note 5 ) i out2 = 300 ma power supply rejection ratio psrr 62 db f 100 hz, i out1 = i out2 = 50 ma, c in = 0 f output noise en 1.8 v/(hz) ? f 1 khz, i out2 =50ma, shdn1 =gnd dc characteristics (continued) electrical characteristics: v in1 =v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l = 4.7 h, v out1 (adj) = 1.8v, i out1 = 100 ma, i out2 = 0.1 ma t a = +25c. boldface specifications apply over the t a range of -40c to +85c . parameters sym min typ max units conditions note 1: the minimum v in has to meet two conditions: v in 2.7v and v in v rx + v dropout, v rx = v r1 or v r2 . 2: v rx is the regulator output voltage setting. 3: tcv out2 = ((v out2max C v out2min ) * 10 6 )/(v out2 * d t ). 4: regulation is measured at a constant junction temperature using low duty-cycle pulse testing. load regulation is tested over a load range from 0.1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1v differential. 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. t a , t j , ja ). exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. 7: the integrated mosfet switches hav e an integral diode from the l x pin to v in , and from l x to p gnd . in cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. thermal protection is not able to limit the junction temperature for these cases. 8: v in1 and v in2 are supplied by the same input source. downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 9 tc1303a/tc1303b/tc1303c/tc1304 output short circuit current (average) i outsc2 240 ma r load2 1 ? wake-up time (from shdn2 mode), (v out2 ) t wk 3 11 0 0 si out1 = i out2 = 50 ma settling time (from shdn2 mode), (v out2 ) t s 100 s i out1 = i out2 = 50 ma power-good (pg) voltage range pg v pg 1.01.2 5 . 5 5.5 vt a = 0c to +70c t a = -40c to +85c v in 2.7 i sink = 100 a pg threshold high (v out1 or v out2 ) v th_h 9 4 96 % of v outx on rising v out1 or v out2 v outx =v out1 or v out2 pg threshold low (v out1 or v out2 ) v th_l 89 92 % of v outx on falling v out1 or v out2 v outx =v out1 or v out2 pg threshold hysteresis (v out1 and v out2 ) v th_hys 2% o f v outx v outx =v out1 or v out2 pg threshold tempco v th / t 30 ppm/c pg delay t rpd 165 s v out1 or v out2 =(v th + 100 mv) to (v th - 100 mv) pg active time-out period t rpu 140 262 560 ms v out1 or v out2 =v th - 100 mv to v th + 100 mv, i sink = 1.2 ma pg output voltage low pg_v ol 0.2 vv out1 or v out2 =v th - 100 mv , i pg = 1.2 ma v in2 >2.7v i pg = 100 a, 1.0v < v in2 < 2.7v pg output voltage high (tc1303b only) pg_v oh 0.9* v out2 vv out1 or v out2 =v th + 100 mv v out2 1.8v, i pg = - 500 a v out2 < 1.8v,i pg = - 300 a dc characteristics (continued) electrical characteristics: v in1 =v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l = 4.7 h, v out1 (adj) = 1.8v, i out1 = 100 ma, i out2 = 0.1 ma t a = +25c. boldface specifications apply over the t a range of -40c to +85c . parameters sym min typ max units conditions note 1: the minimum v in has to meet two conditions: v in 2.7v and v in v rx + v dropout, v rx = v r1 or v r2 . 2: v rx is the regulator output voltage setting. 3: tcv out2 = ((v out2max C v out2min ) * 10 6 )/(v out2 * d t ). 4: regulation is measured at a constant junction temperature using low duty-cycle pulse testing. load regulation is tested over a load range from 0.1 ma to the maximum specified output current. 5: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1v differential. 6: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. t a , t j , ja ). exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. 7: the integrated mosfet switches hav e an integral diode from the l x pin to v in , and from l x to p gnd . in cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. thermal protection is not able to limit the junction temperature for these cases. 8: v in1 and v in2 are supplied by the same input source. downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 10 ? 2008 microchip technology inc. temperature specifications electrical specifications: unless otherwise indicated, all limits are specified for: v in = +2.7v to +5.5v parameters sym min typ max units conditions temperature ranges operating junction temperature range t j -40 +125 c steady state storage temperature range t a -65 +150 c maximum junction temperature t j +150 c transient thermal package resistances thermal resistance, 10l-dfn ja 41 c/w typical 4-layer board with internal ground plane and 2 vias in thermal pad thermal resistance, 10l-msop ja 113 c/w typical 4-layer board with internal ground plane downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 11 tc1303a/tc1303b/tc1303c/tc1304 2.0 typical performance curves note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical performance characteristics. figure 2-1: i q switcher and ldo current vs. ambient temperature (tc1303a,b). figure 2-2: i q switcher and ldo current vs. ambient temperature (tc1303c, tc1304). figure 2-3: i q switcher current vs. ambient temperature. figure 2-4: i q ldo current vs. ambient temperature. figure 2-5: v out1 output efficiency vs. input voltage (v out1 = 1.2v). figure 2-6: v out1 output efficiency vs. i out1 (v out1 = 1.2v). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 60 64 68 72 76 80 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) i q switcher and ldo (a) v in = 3.6v v in = 4.2v v in = 5.5v i out1 = i out2 = 0 ma shdn1 = v in2 shdn2 = v in2 66 68 70 72 74 76 78 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) i q switcher and ldo (a) v in = 5.5v shdn1 = v in2 shdn2 = v in2 v in = 4.2v v in = 3.6v 30 35 40 45 50 55 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) i q switcher (a) v in = 3.6v v in = 4.2v v in = 5.5v i out1 = 0 ma shdn1 = v in2 shdn2 = a gnd 30 35 40 45 50 55 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) i q ldo (a) v in = 3.6v v in = 4.2v v in = 5.5v i out2 = 0 ma shdn1 = a gnd shdn2 = v in2 50 55 60 65 70 75 80 85 90 95 100 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) v out1 efficiency (%) i out1 = 100 ma i out1 = 250 ma i out1 = 500 ma shdn1 = v in2 shdn2 = a gnd 70 75 80 85 90 95 100 0.005 0.104 0.203 0.302 0.401 0.5 i out1 (a) v out1 efficiency(%) v in1 = 3.0v v in1 = 4.2v v in1 = 3.6v shdn1 = v in2 shdn2 = a gnd downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 12 ? 2008 microchip technology inc. note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical perform ance characteristics. figure 2-7: v out1 output efficiency vs. input voltage (v out1 = 1.8v). figure 2-8: v out1 output efficiency vs. i out1 (v out1 = 1.8v). figure 2-9: v out1 output efficiency vs. input voltage (v out1 = 3.3v). figure 2-10: v out1 output efficiency vs. i out1 (v out1 = 3.3v). figure 2-11: v out1 vs. i out1 (v out1 = 1.2v). figure 2-12: v out1 vs. i out1 (v out1 = 1.8v). 60 65 70 75 80 85 90 95 100 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) v out1 efficiency(%) i out1 = 100 ma i out1 = 250 ma i out1 = 500 ma shdn1 = v in2 shdn2 = a gnd 75 80 85 90 95 100 0.005 0.104 0.203 0.302 0.401 0.5 i out1 (a) v out1 efficiency(%) shdn1 = v in2 shdn2 = a gnd v in = 3.0v v in = 4.2v v in = 3.6v 80 84 88 92 96 100 3.60 3.92 4.23 4.55 4.87 5.18 5.50 input voltage (v) v out1 efficiency (%) i out1 = 100 ma i out1 = 250 ma i out1 = 500 ma shdn1 = v in2 shdn2 = a gnd 60 65 70 75 80 85 90 95 100 0.005 0.104 0.203 0.302 0.401 0.5 i out1 (a) v out1 efficiency (%) v in1 = 5.5v shdn1 = v in2 shdn2 = a gnd v in1 = 4.2v v in1 = 3.6v 1.19 1.194 1.198 1.202 1.206 1.21 0.005 0.104 0.203 0.302 0.401 0.5 i out1 (a) v out1 (v) shdn1 = v in2 shdn2 = a gnd v in1 = 3.6v 1.79 1.795 1.8 1.805 1.81 1.815 1.82 0.005 0.104 0.203 0.302 0.401 0.5 i out1 (a) v out1 (v) shdn1 = v in2 shdn2 = a gnd v in1 = 3.6v downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 13 tc1303a/tc1303b/tc1303c/tc1304 note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical performance characteristics. figure 2-13: v out1 vs. i out1 (v out1 = 3.3v). figure 2-14: v out1 switching frequency vs. input voltage. figure 2-15: v out1 switching frequency vs. ambient temperature. figure 2-16: v out1 adjustable feedback voltage vs. ambient temperature. figure 2-17: v out1 switch resistance vs. input voltage. figure 2-18: v out1 switch resistance vs. ambient temperature. 3.2 3.24 3.28 3.32 3.36 3.4 0.005 0.104 0.203 0.302 0.401 0.5 i out1 (a) v out1 (v) shdn1 = v in2 shdn2 = a gnd v in1 = 4.2v 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) v out1 frequency (mhz) shdn1 = v in2 shdn2 = a gnd 1.90 1.92 1.94 1.96 1.98 2.00 -40 -25 -10 5 2035 50 65 80 95 110 125 ambient temperature (c) v out1 frequency (mhz) shdn1 = v in2 shdn2 = a gnd 0.790 0.795 0.800 0.805 0.810 0.815 0.820 -40-25 -10 5 2035 50 65 80 95 110125 ambient temperature (c) v out1 fb voltage (v) shdn1 = v in2 shdn2 = a gnd v in1 = 3.6v 0.3 0.35 0.4 0.45 0.5 0.55 0.6 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) v out1 switch resistance () shdn1 = v in2 shdn2 = a gnd t a = 25 c n-channel p-channel 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) v out1 switch resistance () shdn1 = v in2 shdn2 = a gnd v in1 = 3.6v n-channel p-channel downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 14 ? 2008 microchip technology inc. note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical perform ance characteristics. figure 2-19: v out1 dropout voltage vs. ambient temperature. figure 2-20: v out1 and v out2 heavy load switching waveforms vs. time. figure 2-21: v out1 and v out2 light load switching waveforms vs. time. figure 2-22: v out2 output voltage vs. input voltage (v out2 = 1.5v). figure 2-23: v out2 output voltage vs. input voltage (v out2 = 1.8v). figure 2-24: v out2 output voltage vs. input voltage (v out2 = 2.5v). 0.1 0.15 0.2 0.25 0.3 0.35 0.4 -40 -25 -10 5 2035 50 65 80 95 110 125 ambient temperature (c) v out1 dropout voltage (v) shdn1 = v in2 shdn2 = a gnd v out1 = 3.3 v i out1 = 500 ma 1.482 1.484 1.486 1.488 1.49 1.492 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) v out2 output voltage(v) t a = - 40c t a = + 25c t a = + 85c i out2 = 150 ma shdn1 = a gnd shdn2 = v in2 1.792 1.794 1.796 1.798 1.800 1.802 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) v out2 output voltage (v) t a = - 40c t a = + 25c t a = + 85c i out2 = 150 ma shdn1 = a gnd shdn2 = v in2 2.496 2.498 2.500 2.502 2.504 2.506 2.508 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) v out2 output voltage (v) t a = - 40c t a = + 25c t a = + 85c i out2 = 150 ma shdn1 = a gnd shdn2 = v in2 downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 15 tc1303a/tc1303b/tc1303c/tc1304 note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical performance characteristics. figure 2-25: v out2 output voltage vs. input voltage (v out2 = 3.3v). figure 2-26: v out2 dropout voltage vs. ambient temperature (v out2 = 2.5v). figure 2-27: v out2 dropout voltage vs. ambient temperature (v out2 = 3.3v). figure 2-28: v out2 line regulation vs. ambient temperature. figure 2-29: v out2 load regulation vs. ambient temperature. figure 2-30: pg active delay time-out vs. ambient temperature. 3.292 3.293 3.294 3.295 3.296 3.297 3.298 3.60 3.92 4.23 4.55 4.87 5.18 5.50 input voltage (v) v out2 output voltage (v) t a = - 40c t a = + 25c t a = + 85c i out2 = 150 ma shdn1 = a gnd shdn2 = v in2 0.05 0.10 0.15 0.20 0.25 0.30 -40 -25 -10 5 2035 50 65 80 95 110 125 ambient temperature (c) v out2 dropout voltage (v) i out2 = 200 ma i out2 = 300 ma shdn1 = a gnd shdn2 = v in2 0.0 0.1 0.2 0.3 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) v out2 dropout voltage (v) i out2 = 200 ma shdn1 = a gnd shdn2 = v in2 i out2 = 300 ma -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) v out2 line regulation (%/v) v out2 = 3.3v i out2 = 100 a shdn1 = a gnd shdn2 = v in2 v out2 = 2.5v v out2 = 1.5v -0.4 -0.3 -0.2 -0.1 0.0 0.1 -40 -25 -10 5 2035 50 65 80 95 110 125 ambient temperature (c) v out2 load regulation (%) v out2 = 3.3v v in2 = 3.6v shdn1 = a gnd shdn2 = v in2 v out2 = 2.6v v out2 = 1.5v 200 225 250 275 300 325 350 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) pg active delay time (ms) shdn1 = v in2 shdn2 = v in2 v in = 3.6v downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 16 ? 2008 microchip technology inc. note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical perform ance characteristics. figure 2-31: pg threshold voltage vs. ambient temperature. figure 2-32: pg output voltage level low vs. ambient temperature. figure 2-33: pg output voltage level high vs. ambient temperature. figure 2-34: v out2 power supply ripple rejection vs. frequency. figure 2-35: v out2 noise vs. frequency. figure 2-36: v out1 load step response vs. time. 90 91 92 93 94 95 96 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) pg threshold (% of v out2 ) shdn1 = v in2 shdn2 = v in2 v in = 3.6v pg threshold hi pg threshold low 0.01 0.012 0.014 0.016 0.018 0.02 -40 -25 -10 5 2035 50 65 80 95 110 125 ambient temperature (c) pg v ol (v) v in = 3.6v i ol = 1.2 ma shdn1 = v in2 shdn2 = v in2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 ambient temperature (c) pg v oh (v) v in = 3.6v i oh = 500 a v out2 = 2.8v v out2 = 2.5v v out2 = 1.5v shdn1 = v in2 shdn2 = v in2 -80 -70 -60 -50 -40 -30 -20 -10 0 0.01 0.1 1 10 100 1000 frequency (khz) v out2 psrr (db) shdn1 = gnd v out2 = 1.5v i out2 = 30 ma c in = 0 f c out2 = 1.0 f c out2 = 4.7 f 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 10000 frequency (khz) v out2 noise (v/ hz) shdn1 = a gnd shdn2 = v in2 v in = 3.6v v out2 = 2.5v i out2 = 50 ma downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 17 tc1303a/tc1303b/tc1303c/tc1304 note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical performance characteristics. figure 2-37: v out2 load step response vs. time. figure 2-38: v out1 and v out2 line step response vs. time. figure 2-39: v out1 and v out2 start-up waveforms. figure 2-40: v out1 and v out2 shutdown waveforms. figure 2-41: power-good output timing. figure 2-42: start-up waveforms (tc1304). downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 18 ? 2008 microchip technology inc. note: unless otherwise indicated, v in1 = v in2 = shdn1,2 = 3.6v, c out1 =c in = 4.7 f, c out2 =1f, l =4.7h, v out1 (adj) = 1.8v, t a = +25c. boldface specifications apply over the t a range of -40c to +85c. t a = +25c. adjustable- or fixed- output voltage options can be used to generate the typical perform ance characteristics. figure 2-43: shutdown waveforms (tc1304). downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 19 tc1303a/tc1303b/tc1303c/tc1304 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 tc1303 ldo shutdown input pin (shdn2 ) shdn2 is a logic-level input used to turn the ldo regulator on and off. a logic-high (> 45% of v in ), will enable the regulator output. a logic-low (< 15% of v in ) will ensure that the output is turned off. 3.2 tc1304 shutdown input pin (shdn ) shdn is a logic-level input used to initiate the sequencing of the ldo outpu t, then the buck regulator output. a logic-high (> 45% of v in ), will enable the regulator outputs. a logic-low (< 15% of v in ) will ensure that the outputs are turned off. 3.3 ldo input voltage pin (v in2 ) v in2 is a ldo power input supply pin. connect variable input voltage source to v in2 . connect v in1 and v in2 together with board traces as short as possible. v in2 provides the input voltage for the ldo. an additional capacitor can be added to lower the ldo regulator input ripple voltage. 3.4 ldo output voltage pin (v out2 ) v out2 is a regulated ldo output voltage pin. connect a 1 f or larger capacitor to v out2 and a gnd for proper operation. 3.5 power-good output pin (pg) pg is an output level indicating that v out2 (ldo) is within 94% of regulation. t he pg output is configured as a push-pull for the tc1303b and open-drain output for the tc1303a, tc1303c and tc1304. 3.6 analog ground pin (a gnd ) a gnd is the analog ground connection. tie a gnd to the analog portion of the ground plane (a gnd ). see the physical layout information in section 5.0 application circuits/issues for grounding recommendations. 3.7 buck regulator output sense pin (v fb /v out1 ) for v out1 adjustable-output voltage options, connect the center of the output voltage divider to the v fb pin. for fixed-output voltage options, connect the output of the buck regulator to this pin (v out1 ). pin no. symbol description tc1303 tc1304 msop, dfn msop, dfn 1 shdn2 active low shutdown input for ldo output pin 1 shdn active low shutdown input both buck regulator output and ldo output. initiates sequencing up and down 2v in2 v in2 analog input supply voltage pin 3v out2 v out2 ldo output voltage pin 4 pg pg power-good output pin 5a gnd a gnd analog ground pin 6v fb /v out1 v fb /v out1 buck feedback voltage (adjustable version) / buck output voltage (fixed version) pin 7 shdn1 active low shutdown input for buck regulator output pin 7a gnd analog ground pin 8v in1 v in1 buck regulator input voltage pin 9l x l x buck inductor output pin 10 p gnd p gnd power ground pin 11 ep ep exposed pad - for the dfn package, the center exposed pad is a thermal path to remove heat from the device. electrically this pad is at ground potential and should be connected to a gnd . downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 20 ? 2008 microchip technology inc. 3.8 buck regulator shutdown input pin (shdn1 ) shdn1 is a logic-level input used to turn the buck regulator on and off. a logic-high (> 45% of v in ), will enable the regulator output. a logic-low (< 15% of v in ) will ensure that the output is turned off. 3.9 buck regulator input voltage pin (v in1 ) v in1 is the buck regulator power input supply pin. connect a variable input voltage source to v in1 . connect v in1 and v in2 together with board traces as short as possible. 3.10 buck inductor output pin (l x ) connect l x directly to the buck inductor. this pin carries large signal-level current; all connections should be made as short as possible. 3.11 power ground pin (p gnd ) connect all large-signal level ground returns to p gnd . these large-signal, level ground traces should have a small loop area and length to prevent coupling of switching noise to sensitiv e traces. please see the physical layout information supplied in section 5.0 application circuits/issues for grounding recommendations. 3.12 exposed pad (ep) for the dfn package, connect the ep to a gnd , with vias into the a gnd plane. downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 21 tc1303a/tc1303b/tc1303c/tc1304 4.0 detailed description 4.1 device overview the tc1303/tc1304 combines a 500 ma synchronous buck regulator with a 300 ma ldo and a power-good output. this unique combination provides a small, low-cost solution for applications that require two or more voltage rails. the buck regulator can deliver high-output current over a wide range of input- to-output voltage ratios while maintaining high efficiency. this is typically used for the lower-voltage, high-current processor core. the ldo is a minimal parts-count solution (single-output capacitor), providing a regulated voltage for an auxiliary rail. the typical ldo dropout voltage (137 mv @ 200 ma) allows the use of very low input-to-output ldo differential voltages, minimizing the power loss internal to the ldo pass transistor. a power-good output is provided, indicating that the buck regulator out put, the ldo output or both outputs are in regulation. additional features include independent shutdown inputs (tc1303), uvlo, output voltage sequencing (tc1304), overcurrent and overtemperature shutdown. 4.2 synchronous buck regulator the synchronous buck regulator is capable of supplying a 500 ma continuous output current over a wide range of input and ou tput voltages. the output voltage range is from 0.8v (minimum) to 4.5v (maximum). the regulator operates in three different modes, automatically selecting the most efficient mode of operation. during heavy load conditions, the tc1303/tc1304 buck converter operates at a high, fixed frequency (2.0 mhz) using current mode control. this minimizes output ripple and noise (less than 8 mv peak-to-peak ripple) while maintaining high efficiency (typically > 90%). for standby or light load applications, the buck regulator will automatically switch to a power- saving pulse frequency modulation (pfm) mode. this minimizes the quiescent current draw on the battery, while keeping the buck output voltage in regulation. the typical buck pfm mode current is 38 a. the buck regulator is capable of op erating at 100% duty cycle, minimizing the voltage drop from input-to-output for wide input, battery-powered applications. for fixed- output voltage applications, the feedback divider and control loop compensation components are integrated, eliminating the need for external components. the buck regulator output is protected against overcurrent, short circuit and overtemperature. while shut down, the synchronous buck n-channel and p-channel switches are off, so the l x pin is in a high-impedance state (this allows for connecting a so urce on the output of the buck regulator as long as its voltage does not exceed the input voltage). 4.2.1 fixed-frequency pwm mode while operating in pulse width modulation (pwm) mode, the tc1303/tc1304 buck regulator switches at a fixed, 2.0 mhz frequency. the pwm mode is suited for higher load current operation, maintaining low output noise and high conversion efficiency. pfm-to- pwm mode transition is initiated for any of the following conditions: continuous inductor current is sensed inductor peak current exceeds 100 ma the buck regulator output voltage has dropped out of regulation (step load has occurred) the typical pfm-to-pwm threshold is 80 ma. 4.2.2 pfm mode pfm mode is entered when the output load on the buck regulator is very light. once detected, the converter enters the pfm mode automatically and begins to skip pulses to minimize unnecessary quiescent current draw by reducing the numb er of switching cycles per second. the typical quiescent current for the switching regulator is less than 35 a. the transition from pwm to pfm mode occurs when discontinuous inductor current is sensed or the pe ak inductor current is less than 60 ma (typical). the typical pwm to pfm mode threshold is 30 ma. for low input-to-output differential voltages, the pwm-to-pfm mode threshold can be low due to the lack of ripple current. it is recommended that v in1 be one volt greater than v out1 for pwm-to-pfm transitions. 4.3 low drop out regulator (ldo) the ldo output is a 300 ma low-dropout linear regulator that provides a regulated output voltage with a single 1 f external capacitor. the output voltage is available in fixed options only, ranging from 1.5v to 3.3v. the ldo is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the regulator solution. the quiescent current consumed by the ldo output is typically less than 40 a, with a typical dropout voltage of 137 mv at 200 ma. while operating in dropout mode, the ldo quiescent current will increase, minimizing the necessary voltage differential needed for the ldo output to maintain regulation. the ldo output is protected against overcurrent and overtemperature conditions. downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 22 ? 2008 microchip technology inc. 4.4 power-good a power-good (pg) output signal is generated based off of the buck regulator output voltage (v out1 ), the ldo output voltage (v out2 ) or the combination of both outputs. a fixed delay time of approximately 262 ms is generated once the monitored output voltage is above the power-good threshold (typically 94% of v outx ). as the monitored output voltage falls out of regulation, the falling pg threshold is typically 92% of the output voltage. the pg output signal is pulled up to the output voltage, indicating that power is good and pulled low, indicating that the output is out of regulation. the typical quiescent current draw for power-good circuitry is less than 10 a. if the monitored output voltage falls below the power- good threshold, the power-go od output will transition to the low state. the power-good circuitry has a 165 s delay when detecting a falling output voltage. this helps to increase the noise immunity of the power-good output, avoiding false trigger ing of the pg signal during line and load transients. figure 4-1: power-good timing. 4.5 power good output options there are three monitoring options for the tc1303 family. for the tc1303a, only the buck regulator output voltage (v out1 ) is monitored. the pg output signal depends only on v out1 . for the tc1303b, only the ldo output voltage (v out2 ) is monitored. the pg ou tput signal depends only on v out2 . for the tc1303c and tc1304, both the buck regulator output voltage and ldo output voltage are monitored. if either one of the outputs fall out of regulation, the pg will be low. only if both v out1 and v out2 are within the pg voltage threshold limits will the pg output be high. for the tc1303a,c and tc1304, the pg output pin is open drain and can be pulled up to any level within the given absolute maximum ratings (a gnd - 0.3v) to (v in + 0.3v). table 4-1: pg available options t rpu t rpd v th_h v out1 pg v ol v oh or v out2 part number pg output buck (v out1 ) pg output ldo (v out2 ) pg output type tc1303a yes no open-drain tc1303b no yes push-pull (v out2 ) tc1303c yes yes open-drain tc1304 yes yes open-drain downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 23 tc1303a/tc1303b/tc1303c/tc1304 4.6 tc1304 sequencing the tc1304 device features an integrated sequencing option. a sequencing circuit using only the shdn input, (pin1), will turn on the ldo output (v out2 ) and delay the turn on of the buck regulator output (v out1 ) until the ldo output is in regulation. during power-down, the sequencing circuit will turn off the buck regulator output prior to turning off ldo output. figure 4-2: tc1304 sequencing circuit. figure 4-3: tc1304 power-up timing from shdn . 4.7 soft start both outputs of the tc 1303/tc1304 are controlled during start-up. less than 1% of v out1 or v out2 overshoot is observed during start-up from v in rising above the uvlo voltage or either shdn1 or shdn2 being enabled. 4.8 overtemperature protection the tc1303/tc1304 has an integrated overtempera- ture protection circuit that monitors the device junction temperature and shuts the device off if the junction temperature exceeds the typical 165c threshold. if the overtemperature threshold is reached, the soft start is reset so that, once the junction temperature cools to approximately 155c, the device will automatically restart. enable enable v out2 v out1 + C + C 160 s delay* 160 s delay* 92% of v out2 92% of v out1 to p g delay ckt. shdn * 160 s delay on trailing edge v in1 /v in2 v out1 v out2 power good power up timing from shdn 300 ms t wk + t s 500 s tc1304 shdn downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 24 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 25 tc1303a/tc1303b/tc1303c/tc1304 5.0 application circuits/ issues 5.1 typical applications the tc1303/tc1304 500 ma buck regulator + 300 ma ldo with power-good operates over a wide input volt- age range (2.7v to 5.5v) and is ideal for single-cell li- ion battery-powered applications, usb-powered applications, three-cell nimh or nicd applications and 3v to 5v regulated input applications. the 10-pin msop and 3x3 dfn packages provide a small footprint with minimal external components. 5.2 fixed output application a typical v out1 fixed-output voltage application is shown in typical application circuits . a 4.7 f v in1 ceramic input capacitor, 4.7 f v out1 ceramic capacitor, 1.0 f ceramic v out2 capacitor and 4.7 h inductor make up the entire external component solution for this dual-output application. no external dividers or compensation components are necessary. for this application, the input voltage range is 2.7v to 4.2v, v out1 = 1.5v at 500 ma, while v out2 =2.5v at 300 ma. 5.3 adjustable output application a typical v out1 adjustable output application is also shown in typical application circuits . for this application, the buck regulator output voltage is adjustable by using two external resistors as a voltage divider. for adjustable-output voltages, it is recommended that the top resistor divider value be 200 k ? . the bottom resistor divider can be calculated using the following formula: equation 5-1: example: for adjustable-output applications, an additional r-c compensation is necessary for the buck regulator control loop stability. recommended values are: an additional v in2 capacitor can be added to reduce high-frequency noise on the ldo input voltage pin (v in2 ). this additional capacitor (1 f on page 5) is not necessary for typical applications. 5.4 input and output capacitor selection as with all buck-derived dc-dc switching regulators, the input current is pulled from the source in pulses. this places a burden on the tc 1303/tc1304 input filter capacitor. in most applications, a minimum of 4.7 f is recommended on v in1 (buck regulator input voltage pin). in applications that have high source impedance, or have long leads, (10 inches) connecting to the input source, additional capacitance should be used. the capacitor type can be electrolytic (aluminum, tantalum, poscap, oscon) or cera mic. for most portable electronic applications, ceramic capacitors are preferred due to their small size and low cost. for applications that require very low noise on the ldo output, an additional capacitor (typically 1 f) can be added to the v in2 pin (ldo input voltage pin). low esr electrolytic or ceramic can be used for the buck regulator output capacitor. again, ceramic is recommended because of its physical attributes and cost. for most applications, a 4.7 f is recommended. refer to ta b l e 5 - 1 for recommended values. larger capacitors (up to 22 f) can be used. there are some advantages in load step performance when using larger value capacitors. ceramic materials x7r and x5r have low temperature coefficients and are well within the acceptable esr range required. table 5-1: tc1303a, tc1303b, tc1303c, tc1304 recommended capacitor values r top = 200 k ? v out1 =2.1v v fb =0.8v r bot = 200 k ? x (0.8v/(2.1v C 0.8v)) r bot = 123 k ? (standard value = 121 k ? ) r comp =4.99k ? c comp =33pf r bot r top v fb v out1 v fb C -------------------------------- ?? ?? = c(v in1 )c(v in2 )c out1 c out2 min 4.7 f none 4.7 f 1 f max none none 22 f 10 f downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 26 ? 2008 microchip technology inc. 5.5 inductor selection for most applications, a 4.7 h inductor is recom- mended to minimize noise. there are many different magnetic core materials and package options to select from. that decision is based on size, cost and accept- able radiated energy levels. toroid and shielded ferrite pot cores will have low radiated energy, but tend to be larger and higher is cost. with a typical 2.0 mhz switching frequency, the inductor ripple current can be calculated based on the following formulas. equation 5-2: duty cycle represents the percentage of switch-on time. equation 5-3: the inductor ac ripple current can be calculated using the following relationship: equation 5-4: solving for ? i l = yields: equation 5-5: when considering inductor ratings, the maximum dc current rating of the inductor should be at least equal to the maximum buck regulator load current (i out1 ), plus one half of the peak-to-peak inductor ripple current (1/ 2* i l ). the inductor dc resistance can add to the buck converter i 2 r losses. a rating of less than 200 m ? is recommended. overall efficiency will be improved by using lower dc resistance inductors. table 5-2: tc1303a, tc1303b, tc1303c, tc1304 recommended inductor values 5.6 thermal calculations 5.6.1 buck regulator output (v out1 ) the tc1303/tc1304 is available in two different 10-pin packages (msop and 3x3 dfn). by calculating the power dissipation and applying the package thermal resistance, ( ja ), the junction tem perature is estimated. the maximum continuous junction temperature rating for the tc1303/tc1304 is +125c. to quickly estimate the internal power dissipation for the switching buck regulator, an empirical calculation using measured efficiency can be used. given the measured efficiency ( section 2.0 typical perfor- mance curves ), the internal power dissipation is estimated below: equation 5-6: the first term is equal to the input power (definition of efficiency, p out /p in = efficiency). the second term is equal to the delivered power. the difference is internal power dissipation. this is an estimate assuming that most of the power lost is internal to the tc1303b. there is some percentage of power lost in the buck inductor, with very little loss in the input and output capacitors. dutycycle v out v in ------------- = t on dutycycle 1 f sw --------- - = where: f sw = switching frequency. v l l i l t -------- = where: v l = voltage across the inductor (v in C v out ) ? t = on-time of p-channel mosfet i l v l l ------ t = part number value (h) dcr ? ( max) max i dc (a) size wxlxh (mm) coiltronics ? sd10 2.2 0.091 1.35 5.2, 5.2, 1.0 max. sd10 3.3 0.108 1.24 5.2, 5.2, 1.0 max. sd10 4.7 0.154 1.04 5.2, 5.2, 1.0 max. coiltronics sd12 2.2 0.075 1.80 5.2, 5.2, 1.2 max. sd12 3.3 0.104 1.42 5.2, 5.2, 1.2 max. sd12 4.7 0.118 1.29 5.2, 5.2, 1.2 max. sumida corporation ? cmd411 2.2 0.116 0.950 4.4, 5.8, 1.2 max. cmd411 3.3 0.174 0.770 4.4, 5.8, 1.2 max. cmd411 4.7 0.216 0.750 4.4, 5.8, 1.2 max. coilcraft ? 1008ps 4.7 0.35 1.0 3.8, 3.8, 2.74 max. 1812ps 4.7 0.11 1.15 5.9, 5.0, 3.81 max v out1 i out1 efficiency ------------------------------------- ?? ?? v out1 i out1 () C p dissipation = downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 27 tc1303a/tc1303b/tc1303c/tc1304 as an example, for a 3.6v input, 1.8v output with a load of 400 ma, the efficiency taken from figure 2-8 is approximately 84%. the internal power dissipation is approximately 137 mw. 5.6.2 ldo output (v out2 ) the internal power dissipation within the tc1303/ tc1304 ldo is a function of input voltage, output voltage and output current. equation 5-7 can be used to calculate the internal power dissipation for the ldo. equation 5-7: the maximum power dissipa tion capability for a package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient temperature for t he application. the following equation can be used to determine the packages maximum internal power dissipation. 5.6.3 ldo power dissipation example 5.7 pcb layout information some basic design guidelines should be used when physically placing the tc1303/tc1304 on a printed circuit board (pcb). the tc1303/tc1304 has two ground pins, identified as a gnd (analog ground) and p gnd (power ground). by separating grounds, it is possible to minimize the switching frequency noise on the ldo output. the first priority, while placing external components on the board, is the input capacitor (c in1 ). wiring should be short and wide; the input current for the tc1303/tc1304 can be as high as 800 ma. the next priority would be the buck regulator output capacitor (c out1 ) and inductor (l 1 ). all three of these components are placed near their respective pins to minimize trace length. the c in1 and c out1 capacitor returns are connected closely together at the p gnd plane. the ldo optional input capacitor (c in2 ) and ldo output capacitor c out2 are returned to the a gnd plane. the analog ground plane and power ground plane are connected at one point (shown near l 1 ). all other signals (shdn1 , shdn2 , feedback in the adjustable-output case) should be referenced to a gnd and have the a gnd plane underneath them. figure 5-1: component placement, fixed 10-pin msop. there will be some difference in layout for the 10-pin dfn package due to the thermal pad. a typical fixed- output dfn layout is shown below. for the dfn layout, the v in1 to v in2 connection is rout ed on the bottom of the board around the tc1303/tc1304 thermal pad. figure 5-2: component placement, fixed 10-pin dfn. input voltage v in =5v10% ldo output voltage and current v out =3.3v i out = 300 ma internal power dissipation p ldo(max) =(v in(max) C v out2(min) ) x i out2(max) p ldo = (5.5v C 0.975 x 3.3v) x 300 ma p ldo = 684.8 mw p ldo v in max ) () v out2 min () C () i out2 max ) () = where: p ldo = ldo pass device internal power dissipation v in(max) = maximum input voltage v out(min) = ldo minimum output voltage tc1303b 12 6 8 7 9 10 5 4 3 +v out1 p gnd +v in1 a gnd a gnd +v out2 c out1 c in2 c o u t 2 c i n 1 p gnd plane a gnd plane l 1 a gnd to p gnd +v in2 * c in2 optional - via 1 2 6 8 7 9 10 5 4 3 +v out1 p gnd +v in1 a gnd a gnd +v out2 c out1 c in2 c o u t 2 c i n 1 p gnd plane a gnd plane l 1 a gnd to p gnd pgnd * c in2 optional +v in2 tc1303b - via downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 28 ? 2008 microchip technology inc. 5.8 design example v out1 = 2.0v @ 500 ma v out2 = 3.3v @ 300 ma v in = 5v10% l = 4.7h calculate pwm mode inductor ripple current nominal duty cycle = 2.0v/5.0v = 40% p-channel switch-on time = 0.40 x 1/(2 mhz) = 200 ns v l =(v in -v out1 )=3v ? i l =(v l /l) x t on =128ma peak inductor current: i l(pk) =i out1 +1/2 ? i l = 564 ma switcher power loss: use efficiency estimate for 1.8v from figure 2-8 efficiency = 84%, p diss1 =190mw resistor divider: r top =200k ? r bot =133k ? ldo output: p diss2 =(v in(max) C v out2(min) )xi out2(max) p diss2 = (5.5v C (0.975) x 3.3v) x 300 ma p diss2 =684.8mw to ta l dissipation = 190 mw + 685 mw = 874 mw junction temp rise and maximum ambient operating temperat ure calculations 10-pin msop (4-layer board with internal planes) r ja =113c/watt junction temp. rise = 874 mw x 113 c/watt = 98.8c max. ambient temperature = 125c - 98.8c max. ambient temperature = 26.3c 10-pin dfn r ja = 41 c/watt (4-layer board with internal planes and 2 vias) junction temp. rise = 874 mw x 41 c/watt = 35.8c max. ambient temperature = 125c - 35.8c max. ambient temperature = 89.2c this is above the +85c ma x. ambient temperature. downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 29 tc1303a/tc1303b/tc1303c/tc1304 6.0 packaging information 6.1 package marking information second letter represents v out1 configuration: third letter represents v out2 configuration: fourth letter represents +50 mv increments: 10-lead msop example: 11h0 0831 256 example: 11h0e 831256 10-lead dfn xxxx yyww nnn 1 = tc1303b 2 = tc1303a 3 = tc1303c 4 = tc1304 1 = 1.375v v out1 h = 2.6v v out2 0 = default xxxxxx ywwnnn code v out1 code v out1 code v out1 a3 . 3 vj2 . 4 vs1 . 5 v b3 . 2 vk2 . 3 vt1 . 4 v c 3.1v l 2.2v u 1.3v d 3.0v m 2.1v v 1.2v e 2.9v n 2.0v w 1.1v f 2.8v o 1.9v x 1.0v g2 . 7 vp1 . 8 vy0 . 9 v h 2.6v q 1.7v z adj i 2.5v r 1.6v 1 1.375v code v out2 code v out1 code v out2 a3 . 3 vj2 . 4 vs1 . 5 v b3 . 2 vk2 . 3 vt c 3.1v l 2.2v u d 3.0v m 2.1v v e 2.9v n 2.0v w f 2.8v o 1.9v x g2 . 7 vp1 . 8 vy h 2.6v q 1.7v z i 2.5v r 1.6v code code 0 default 2 +50 mv to v2 1 +50 mv to v1 3 +50 mv to v1 and v2 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 30 ? 2008 microchip technology inc.

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? 2008 microchip technology inc. ds21949c-page 33 tc1303a/1303b/1303c/1304 appendix a: revision history revision c (december 2008) the following is the list of modifications: 1. updated package types diagram and section 3.0 pin descriptions to show the exposed thermal pad (ep) information. 2. updated section 6.0 packaging informa- tion . revision b (july 2005) the following is the list of modifications: 1. added information on tc1303a, tc1303c and tc1304 throughout data sheet. revision a (june 2005) original release of this document. downloaded from: http:///
tc1303a/1303b/1303c/1304 ds21949c-page 34 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 35 tc1303a/tc1303b/tc1303c/tc1304 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: tc1303a: pwm/ldo combo with power-good tc1303b: pwm/ldo combo with power-good tc1303c: pwm/ldo combo with power-good tc1304: pwm/ldo combo with power-good options code v out1 code v out2 code +50 mv ab cd e f g h i j k l m n o p q r s t u v w xy z 1 3.3v 3.2v 3.1v 3.0v 2.9v 2.8v 2.7v 2.6v 2.5v 2.4v 2.3v 2.2v 2.1v 2.0v 1.9v 1.8v 1.7v 1.6v 1.5v 1.4v 1.3v 1.2v 1.1v 1.0v 0.9v adjustable 1.375v ab cd e f g h i j k l m n o p q r s t u v w xy z 1 3.3v 3.2v 3.1v 3.0v 2.9v 2.8v 2.7v 2.6v 2.5v 2.4v 2.3v 2.2v 2.1v 2.0v 1.9v 1.8v 1.7v 1.6v 1.5v 01 2 3 default +50 mv to v1 +50 mv to v2 +50 mv to v1 and v2 * contact factory for alternate output voltage and reset voltage configurations. temperature range: e = -40c to +85c package: mf = dual flat, no lead (3x3 mm body), 10-lead un = plastic micro small outline (msop), 10-lead tube or tape and reel: blank = tube tr = tape and reel examples: a) tc1303a-si0emf: 1.5v, 2.5v, default, 10ld dfn pkg. b) tc1303a-za0eun: adj, 3.3v, default, 10ld msop pkg. c) tc1303a-pp3emftr: 1.8v, 1.8v, +50 mv, 10ld dfn pkg. tape and reel a) tc1303b-1h0emf: 1.375v, 2.6v, default, 10ld dfn pkg. b) tc1303b-ag0eun: 3.3v, 2.7v, default, 10ld msop pkg. c) tc1303b-ad0emf: 3.3v, 3.0v, default, 10ld dfn pkg. d) tc1303b-ia0eun: 2.5v, 3.3v, default, 10ld msop pkg. e) tc1303b-ia0emf: 2.5v, 3.3v, default, 10ld dfn pkg. f) tc1303b-pf0eun: 1.8v, 2.8v, default, 10ld msop pkg. g) tc1303b-pf0emf: 1.8v, 2.8v, default, 10ld dfn pkg. h) tc1303b-pg0eun: 1.8v, 2.7v, default, 10ld msop pkg. i) tc1303b-dg0emftr: 3.0v, 2.7v, default, 10ld dfn pkg. tape and reel a) tc1303c-vp0emf: 1.2v, 1.8v, default, 10ld dfn pkg. b) tc1303c-vp0emftr: 1.2v, 1.8v, default, 10ld dfn pkg. tape and reel. a) tc1304-vi0emf: 1.2v, 2.5v, default, 10ld dfn pkg. b) tc1304-vp0emf: 1.2v, 1.8v, default, 10ld dfn pkg. c) tc1304-vi0eun: 1.2v, 2.5v, default, 10ld msop pkg. d) tc1304-vi0emftr: 1.2v, 2.5v, default, 10ld dfn pkg. tape and reel. e) tc1304-vp0emftr: 1.2v, 1.8v, default 10ld dfn pkg. tape and reel. f) tc1304-vi0euntr: 1.2v, 2.5v, default, 10ld msop pkg. tape and reel. part no. x- x v out1 type b tc1303 x v out2 x +50 mv increments x temp range xx package xx tube or tape & reel downloaded from: http:///
tc1303a/tc1303b/tc1303c/tc1304 ds21949c-page 36 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds21949c-page 37 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic, smartshunt and uni/o are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
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